Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to an anti-fuse circuit and a semiconductor integrated circuit including the same.
Hereinafter, a semiconductor memory device is explained as a semiconductor integrated circuit in the preferred embodiment.
As semiconductor memory devices are being integrated with high density, the number of signal lines and memory cells included in a semiconductor memory device is increasing rapidly, and the line width of an internal circuit and the size of a memory cell are decreasing gradually due to space limitations, and thus, the possibility of a defect in a memory cell of a semiconductor memory device increases. Despite the increasing possibility of cell defects, semiconductor memory devices can be produced with a high yield by having a redundancy circuit for repairing defective memory cells. The redundancy circuit includes redundancy memory cells and fuses for programming repair addresses corresponding to defective memory cells.
In using redundancy circuits, a number of tests are performed upon completion of a wafer process. At this time, a memory cell, which is determined to be defective but reparable, is replaced with a redundancy memory cell. More specifically, a programming operation is performed in an internal circuit to replace an address corresponding to a defective memory cell with an address of a redundancy memory cell. Thus, when the address corresponding to the defective memory cell is input, the defective memory cell is replaced with the redundancy memory cell, so that the memory device can perform a normal operation. A fuse programming method may be used to program address information corresponding to a defective memory cell. An example of the fuse programming method is a physical fuse programming method that blows out a connected fuse using a laser beam.
However, the physical fuse programming method using a laser beam is possible only in a wafer state before a semiconductor memory device is packaged. Thus, instead of the physical programming method, an electrical programming method may be used to replace a defective memory cell with a redundancy memory cell in a package state. A fuse programmable in a package state is called an electrical fuse. An electrical fuse can be programmed by electrically changing the connection state of the electrical fuse. The electrical fuse comprises an anti-type fuse, which is also referred to as an ‘anti-fuse.’
In general, the anti-fuse operates in opposite to a fuse. At an initial stage for fabricating a semiconductor memory device, the anti-type fuse maintains an open state. When a programming operation is performed, the anti-type fuse changes from the open state to a short-circuit state. More specifically, the anti-fuse at the initial stage for fabricating the semiconductor memory device acts as an insulator in a high resistivity state with resistance greater than 10 MΩ, and then, by programming, the anti-fuse becomes a conductor in a low resistivity state with resistance lower than hundreds of ohms. Here, the anti-fuse is physically changed into a conductor by applying a voltage greater than a predetermined level to an insulator between electrodes, i.e., two conductors, and breaking down the insulator.
FIG. 1 shows a block diagram of a conventional semiconductor memory device including an anti-fuse circuit.
Referring to FIG. 1, the conventional semiconductor memory device 100 includes a plurality of anti-fuse sections 110_1 to 110_N and an anti-fuse information sum-up section 120. The anti-fuse sections 110_1 to 110_N output a plurality of anti-fuse information signals HIT1 to HITN, and the anti-fuse information sum-up section 120 outputs a redundancy enable signal REDEN in response to the anti-fuse information signals HIT1 to HITN.
Hereinafter, since all of the anti-fuse sections 110_1 to 110_N have substantially the same structure, only the first anti-fuse section 110_1 is explained for illustration purposes.
The first anti-fuse section 110_1 includes an anti-fuse 111, a driving unit 112, a switching unit 113, an anti-fuse status detecting unit 114, and a comparing unit 115. The anti-fuse 111 is coupled to a sensing node SN, the driving unit 112 ruptures the anti-fuse 111 in response to a rupture enable signal RUPEN. The anti-fuse status detecting unit 114 outputs an anti-fuse status detecting signal RUPON in response to variation of a voltage at the sensing node SN corresponding to a rupture status of the anti-fuse 111. The switching unit 113 connects or disconnects the driving unit 112 to/from the anti-fuse status detecting unit 114 in response to the rupture enable signal RUPEN, thereby selectively transferring the voltage at the sensing node SN to the anti-fuse status detecting unit 114 as an anti-fuse status signal FUSE_RUP. The comparing unit 115 compares the anti-fuse status detecting signal RUPON with an address signal ADDRESS to output a first anti-fuse information signal HIT1.
FIG. 2 shows a detailed circuit diagram of the anti-fuse 111, the driving unit 112, the switching unit 113, and the anti-fuse status detecting unit 114 included in the first anti-fuse section 110_1.
Referring to FIG. 2, the anti-fuse 111 comprises an NMOS transistor N1 whose gate is coupled to the sensing node SN and source and drain are coupled to a low voltage supply terminal VBBF in common. Here, a ground voltage VSS is supplied to the low voltage supply terminal VBBF when the rupture enable signal RUPEN is inactivated, and a back bias voltage VBB having a voltage level lower than the ground voltage VSS is supplied to the low voltage supply terminal VBBF when the rupture enable signal RUPEN is activated.
The driving unit 112 comprises a first inverter INV1 and a pull-up driving unit P1. The first inverter INV1 inverts the rupture enable signal RUPEN to output a pull-up driving signal RUPENB, the pull-up driving unit P1 couples the sensing node SN to a first high voltage (VPP) supply terminal VPPF in response to the pull-up driving signal RUPENB. Here, the pull-up driving unit P1 includes a first PMOS transistor having a gate receiving the pull-up driving signal RUPENB and a source-drain path coupled between the first high voltage supply terminal VPPF and the sensing node SN.
The switching unit 113 comprises a transmission gate TG1 which selectively outputs the voltage at the sensing node SN as the anti-fuse status signal FUSE_RUP in response to the rupture enable signal RUPEN and the pull-up driving signal RUPENB.
The anti-fuse status detecting unit 114 comprises a NOR gate NOR1 and a second PMOS transistor P2. The NOR gate NOR1 performs a NOR operation on the anti-fuse status signal FUSE_RUP and a power up signal PWRUP to output the anti-fuse status detecting signal RUPON. The second PMOS transistor P2 has a gate receiving the anti-fuse status detecting signal RUPON, and a source-drain path between a second high voltage (VDD) supply terminal VDDF and an output terminal of the switching unit 113. Herein, the second high voltage supply terminal VDDF supplies a second high voltage VDD having a voltage level lower than a first high voltage VPP supplied from the first high voltage supply terminal VPPF.
Although not shown, the comparing unit 115 outputs the first anti-fuse information signal HIT1 of a logic high level when the anti-fuse status detecting signal RUPON has the same logic level as the address signal ADDRESS. The comparing unit 115 outputs the first anti-fuse information signal HIT1 of a logic low level when the anti-fuse status detecting signal RUPON has a logic level different from the address signal ADDRESS.
Hereinafter, an operation of the conventional semiconductor memory device including the anti-fuse circuit is explained in detail.
FIG. 3 is a waveform diagram illustrating an operation of the conventional semiconductor memory device including the anti-fuse circuit shown in FIG. 1.
First, when the rupture enable signal RUPEN is inactivated to a logic low level, the ground voltage VSS is supplied to the source and drain of the NMOS transistor N1 through the low voltage supply terminal VBBF. The pull-up driving unit P1 is disabled while the switching unit 113 maintains a turn-on state. ({circle around (1)})
When the power up signal PWRUP is activated, the anti-fuse status detecting unit 114 outputs the anti-fuse status detecting signal RUPON of a logic low level. ({circle around (1)}) In detail, since the NOR gate NOR1 included in the anti-fuse status detecting unit 114 receives the power up signal PWRUP of a logic high level, the NOR gate NOR1 outputs the anti-fuse status detecting signal RUPON of a logic low level regardless of a logic level of the anti-fuse status signal FUSE_RUP. Subsequently, the second PMOS transistor P2 drives the sensing node SN to the second high voltage VDD in response to the anti-fuse status detecting signal RUPON of a logic low level. More specifically, the sensing node SN is precharged to the second high voltage VDD according as the power up signal PWRUP is activated. Thereafter, even if the power up signal PWRUP is inactivated to a logic low level, the anti-fuse status detecting unit 114 maintains the anti-fuse status detecting signal RUPON of a logic low level by a latch operation. ({circle around (3)})
Then, the rupture enable signal RUPEN is activated, the back bias voltage VBB whose voltage level is lower than the ground voltage VSS is supplied to the source and drain of the NMOS transistor N1 through the low voltage supply terminal VBBF. The pull-up driving unit P1 is enabled while the switching unit 113 enters a turn-off state. Accordingly, the anti-fuse 111 is ruptured due to a high voltage difference between two terminals, i.e., the first voltage VPP is supplied to one terminal and the back bias voltage VBB is supplied to the other terminal. During the above “rupture” process, the anti-fuse 111 becomes a low resistivity state from a high resistivity state so that the low voltage supply terminal VBBF is coupled to the sensing node SN by breaking a gate oxide layer of the NMOS transistor N1 included in the anti-fuse 111. ({circle around (4)})
After completing the “rupture” process, the rupture enable signal RUPEN is inactivated. The ground voltage VSS is supplied to the source and drain of the NMOS transistor N1 through the low voltage supply terminal VBBF. The pull-up driving unit P1 is disabled while the switching unit 113 maintains a turn-on state. Accordingly, the anti-fuse status detecting unit 114 outputs the anti-fuse status detecting signal RUPON of a logic high level based on the anti-fuse status signal FUSE_RUP of a logic low level according to the ground voltage VSS supplied to the source and drain of the NMOS transistor N1 through the low voltage supply terminal VBBF. ({circle around (5)})
Thereafter, the power up signal PWRUP is activated and the anti-fuse status detecting signal RUPON is temporarily transited to a logic low level. ({circle around (6)}) After the power up signal PWRUP is inactivated, the anti-fuse status detecting unit 114 maintains the anti-fuse status detecting signal RUPON of a logic high level since the sensing node SN is coupled to the low voltage supply terminal VBBF supplying the ground voltage VSS. ({circle around (7)})
When the address signal ADDRESS is input, the comparing unit 115 outputs the first anti-fuse information signal HIT1 by comparing the address signal ADDRESS with the anti-fuse status detecting signal RUPON. For example, the comparing unit 115 outputs the first anti-fuse information signal HIT1 of a logic high level when the anti-fuse status detecting signal RUPON has the same logic level as the address signal ADDRESS. On the other hand, the comparing unit 115 outputs the first anti-fuse information signal HIT1 of a logic low level when the anti-fuse status detecting signal RUPON has a logic level different from the address signal ADDRESS.
The other anti-fuse sections 110_2 to 110_N performs substantially the same operation as that of the first anti-fuse section 110_1 to output second to N-th anti-fuse information signals HIT2 to HITN.
The anti-fuse information sum-up section 120 outputs the redundancy enable signal REDEN in response to the anti-fuse information signals HIT1 to HITN. For example, the anti-fuse information sum-up section 120 activates the redundancy enable signal REDEN when all of the anti-fuse information signals HIT1 to HITN are activated to a logic high level. On the other hand, the anti-fuse information sum-up section 120 inactivates the redundancy enable signal REDEN when any of the anti-fuse information signals HIT1 to HITN is inactivated to a logic low level.
As described above, the conventional semiconductor memory device including the anti-fuse circuit can repair defective memory cells in a package state, thereby achieving a high yield of the semiconductor memory device.
However, after the “rupture” process, impedance of the anti-fuse 111 included in the conventional semiconductor memory device increases as time elapses. More specifically, the broken gate oxide layer of the NMOS transistor N1 is slowly restored again as time elapses. At this time, as soon as the “rupture” process is finished, the anti-fuse status detecting signal RUPON is output normally. However, after a predetermined time elapses, an abnormal anti-fuse status detecting signal RUPON may be output.